The fabrication of microcircuit devices on a semiconductor wafer involves a number of steps where patterns are transferred from photolithographic masks onto the wafer. The masking step includes an etching step and defines selected areas to be exposed on the wafer for subsequent processes such as oxidation, metal deposition, and impurity introduction.
In the production of integrated circuit structures, it has become increasingly important to provide structures having a plurality of metallization layers due to the ever increasing density of the circuit elements in the structure. Further, as the device and feature sizes becoming smaller, it is important that the photolithographic mask be aligned precisely with the wafer during the masking step to minimize the misalignment between layers. Most alignment schemes require the use of alignment targets that were defined on the wafers in the previous layer. One such scheme involves the use of two alignment targets that were defined on the wafers with all subsequent layers being aligned with respect to these two alignment targets. Typically, each alignment target comprises topographical marks which can be formed by etching into the wafer a plurality of steps with a height of, for example, 1000 angstrom, and a width and a spacing between each step of, for example, 10 .mu.m. The alignment targets are used to diffract a laser alignment beam generated by a photolithography machine, commonly known as a wafer stepper, during the masking process. The diffraction pattern is received by the wafer stepper and the relative position of the wafer and the photolithographic mask is adjusted accordingly so that the patterns from the photolithographic mask are transferred to the wafer in the precise location as desired.
During the fabrication of the integrated circuit structures, a number of metallization layers are formed. Each of the metallization layers is typically separated from another metallization layer by an insulation layer, such as an oxide layer. In order to minimize the misalignment between layers, it is important that the topography of these alignment targets be replicated from one layer to the next, since the locations of the resulting patterns on each layer are formed based on the precise registration between the photolithographic mask and the alignment targets on the previous layer.
To provide an overlying metallization layer without discontinuities or other flaws, it is desirous to provide an underlying surface for the metallization layer that is as flat or planar as possible. It has, therefore, become the practice to smooth the surface of a layer in preparation for a subsequently applied metallization layer by a process of planarization.
Conventional planarization techniques, such as plasma etching or Reactive Ion Etching (RIE) of oxides with a resist planarizing medium, are used to provide a smooth surface and a local planarization with a range of typically less than 1 .mu.m. Smoothing is achieved over a greater range, but the step topography of the alignment targets is preserved since its step spacing is much greater than the planarization range.
However, to meet the demand for more metal and insulating layers in devices and the stringent depth of focus requirement for submicron lithography, a new planarization technique, commonly known as chemical-mechanical polishing (CMP), is used. U.S. Pat. No. 4,944,836, entitled "Chem-Mech Polishing Method For Producing Coplanar Metal/Insulator film On A Substrate" (issued Jul. 31, 1990, to Beyer et al. and assigned to International Business Machines Corporation) discloses one such CMP technique. Typically, CMP planarization of a wafer involves holding the wafer against a rotating polishing pad wet with a silica-based alkaline slurry and at the same time applying pressure. Unlike the conventional planarization techniques, the CMP planarization technique provides a global planarization, that is, one that provides a large planarization range that generally covers the whole wafer surface. Since the planarization range is large, the alignment targets on a newly formed layer on the wafer will lose its steps after it is planarized by the CMP technique and thus fails to replicate the alignment targets on the previous layer that was beneath the newly formed layer. This is acceptable as long as the planarized newly formed layer is transparent, such as in the case of an oxide, since the laser alignment beam from a wafer stepper and the corresponding diffraction pattern can pass through such transparent layer. However, when the planarized newly formed layer is highly reflective or opaque, such as in the case of a metal, the alignment targets will not be visible to the wafer stepper. In that case, new alignment targets have to be formed on the newly formed layer using a process commonly known as a "window mask" process.
Performed after CMP planarization and before contact masking, a window mask process is a process in which only the alignment targets are exposed, while the rest of the wafer surface is covered by photoresist. The wafer is then subject to an oxide etch of sufficient duration so that the amount of oxide removed during this etch, plus the amount of oxide to be removed during subsequent contact etch, will expose the step patterns of the underlying alignment targets. Thus, when metal is deposited, it replicates the topography of the step patterns of the underlying alignment targets, forming a new set of alignment targets. Accordingly, the wafer stepper can now perform alignment between a photolithographic mask and the wafer in the next photolithographic process.
However, the additional window mask and etch steps, plus their attendant cleanings and inspections, undesirably increase cycle time and process complexity and also introduce particles and defects, resulting in an increase in cost and yield loss. Hence, there is a need to provide an apparatus, a metal deposition system and a method for use in semiconductor fabrication process that utilize CMP planarization prior to metal deposition, while at the same time eliminating the window mask and etch steps. The present invention addresses such a need.